Flip-flops | Readstall

Flip-flops

02-02-19 Mounika Mayakuntla 0 comment

Flip-flops:

          The majority of applications of digital logic require the storage of information. For example, a circuit that controls a combination lock must remember the sequence in which the digits are dialed in order to determine whether to open the lock. Another important example is the storage of programs and data in the memory of a digital computer.

          “The storage elements employed in clocked sequential circuit is called as flip-flops”. The storage capacity of a flip-flop is one bit. Flip-flops are divided into 5 types based on number of outputs. They are

  • SR flip-flop
  • D flip-flop
  • JK flip-flop
  • T flip-flop
  • Edge triggered flip-flop

Each flip-flop has two outputs

  • One for normal value
  • One for complement value of the bit stored in it.
  1. SR flip-flop: It stands for Set-Reset flip-flop. Many applications require that the time at which a latch is set or reset be controlled from an input other than R and S, termed a Clock input. The resultant configuration is called a SR flip-flop.

Operations :

  • If there is no signal at the clock input ‘C’, the output can’t change.
  • When clock signal changes from zero to one depending on the values of S and R the output is going to change.
  • If S=0 and R=0 the output doesn’t change.
  • If S=0 and R=1 the output is zero
  • If =1 and R=0 the output is One
  • If S=1 and R=1 the output is indeterminate.

Characteristic table:

            Inputs                outputs
      S          R             Q(t+1)
      0

0

1

1

          0

1

0

1

    Q(t), No change

0, Clear to zero

1, Set to one

?,  Indeterminate

Graphic symbol:


The main drawback is if S=1 and R=1 then the result is indeterminate so, for this purpose we have D Flip-flop.

  1. D flip-flop:

                 It stands for Data flip-flop. In this case the two signals S and R are derived from a single input D.

Operations:

  • If D=0 the result is zero
  • If D=1 the result is one
  • If there is no signal at the clock input c, the output can not change.

Characteristic table:

      Input        Output
         D             Q(t+1)
          0

1

         0,clear to 0

1,set to one

We can conclude that Q(t+1)=D

Graphic symbol:

  1. JK flip-flop:

          It combines the behaviors of SR and T flip-flops. So that J and K correspond to S and R. for the input valuation J=K=1, the next state is defined as the complement of the present state of the flip-flop i.e., when J=K=1, the flip-flop functions as a toggle, reversing its present state. It is versatile. It can be used to store the data just like D flip-flop. It can also be used to build counters, because it behaves like the T flip-flop if it’s J and K terminals are connected together.

Operations:

Operations  :

  • If there is no signal at the clock input ‘C’, the output can’t change.
  • When clock signal changes from zero to one depending on the values of J and K the output is going to change.
  • If J=0 and K=0 the output doesn’t change.
  • If J=0 and K=1 the output is zero
  • If J=1 and K=0 the output is One
  • If J=1 and K=1 the output is complement of Q(t).

Characteristic table:

            Inputs                outputs
       J          K               Q(t+1)
        0

0

1

1

           0

1

0

1

       Q(t), No change

0, Clear to zero

1, Set to one

Complement value of Q(t)

Graphic symbol:

T flip-flop:

It stands for Toggle flip-flop. Counter circuits are implemented efficiently by using T flip-flops. It changes its state every clock cycle if it’s input T=1. We say that it “toggle” it’s state.

Operations:

  • If there is no signal at clock input C, the output can’t change
  • If T=0 then the output does not change
  • If T=1 then the output becomes the complement of Q(t)

Characteristic table:

      Input        Output
         T             Q(t+1)
          0

1

         Q(t)=0

Q’(t)=1

Graphic symbol:

 

 

          *   If T=0 -> T(J=K=0)=0

*  If T=1 -> t(J=K=1)=1

  1. Edge triggered flip-flop:

           It is also known as Master-Slave flip-flop. It is defined as if data present at the input are transferred to output only at a transition in the clock signal. The input and output are isolated from each other at all other times. The positive edge triggered flip-flop is also known as Master flip-flop place at 0-1 and negative edge triggered flip-flop is also known as Slave flip-flop placed at 1-0. For proper operation, edge triggered flip-flops require the triggering edge of clock pulse to be well defined and to have a very short transition time.

Graphic symbol:

 



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